View MAX17505_8051665.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the MAX17505 high-efficiency, high-voltage, synchro - nously rectified step-down converter with dual integrated mosfets operates over a 4.5v to 60v input. it delivers up to 1.7a and 0.9v to 90%v in output voltage. built-in compensation across the output voltage range eliminates the need for external components. the feedback (fb) regulation accuracy over -40 n c to +125 n c is 1.1%. the device is available in a compact (4mm x 4mm) tqfn lead(pb)-free package with an exposed pad. simulation models are available. the device features a peak-current-mode control architecture with a mode feature that can be used to operate the device in pulse-width modulation (pwm), pulse-frequency modulation (pfm), or discontinuous- conduction mode (dcm) control schemes. pwm operation provides constant frequency operation at all loads, and is useful in applications sensitive to switching frequency. pfm operation disables negative inductor current and additionally skips pulses at light loads for high efficiency. dcm features constant frequency operation down to lighter loads than pfm mode, by not skipping pulses but only disabling negative inductor current at light loads. dcm operation offers efficiency performance that lies between pwm and pfm modes. the low-resistance, on-chip mosfets ensure high efficiency at full load and simplify the layout. a programmable soft-start feature allows users to reduce input inrush current. the device also incorporates an output enable/undervoltage lockout pin (en/uvlo) that allows the user to turn on the part at the desired input- voltage level. an open-drain reset pin provides a delayed power-good signal to the sys tem upon achieving successful regulation of the output voltage. applications industrial power supplies distributed supply regulation base station power supplies wall transformer regulation high-voltage single-board systems general-purpose point-of-load benefts and features eliminates external components and reduces total cost ? no schottky-synchronous operation for high efficiency and reduced cost ? internal compensation for stable operation at any output voltage ? all-ceramic capacitor solution: ultra-compact layout with as few as eight external components reduces number of dc-dc regulators to stock ? wide 4.5v to 60v input voltage range ? 0.9v to 90%v in output voltage ? delivers up to 1.7a over temperature ? 200khz to 2.2mhz adjustable frequency with external synchronization ? available in a 20-pin, 4mm x 4mm tqfn package reduces power dissipation ? peak efficiency > 90% ? pfm and dcm modes for high light-load efficiency ? shutdown current = 2.8 f a (typ) operates reliably ? hiccup-mode current limit and autoretry startup ? built-in output-voltage monitoring (open-drain reset pin) ? resistor-programmable en/uvlo threshold ? adjustable soft-start and prebiased power-up ? -40 n c to +125 n c operation 19-6907; rev 0; 1/14 ordering information appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maximintegrated.com/MAX17505.related . visit www.maximintegrated.com/products/patents for product patent marking information. evaluation kit available MAX17505 4.5v-60v, 1.7a, high-efficiency, synchronous step-down dc-dc converter with internal compensation
maxim integrated 2 electrical characteristics (v in = v en/uvlo = 24v, r rt = 40.2k i (500khz), c vcc = 2.2f, v pgnd = v sgnd = v mode = v sync = 0v, lx = ss = reset = open, v bst to v lx = 5v, v fb = 1v, t a = t j = -40oc to +125oc, unless otherwise noted. typical values are at t a = +25oc. all voltages are referenced to sgnd, unless otherwise noted.) (note 2) note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . v in to pgnd ......................................................... -0.3v to +65v en/uvlo to sgnd ............................................... -0.3v to +65v lx to pgnd ................................................ -0.3v to (v in + 0.3v) bst to pgnd ........................................................ -0.3v to +70v bst to lx ............................................................. -0.3v to +6.5v bst to v cc ........................................................... -0.3v to +65v fb, cf, reset , ss, mode, sync, rt to sgnd ..................................................... -0.3v to +6.5v v cc to sgnd ....................................................... -0.3v to +6.5v sgnd to pgnd .................................................... -0.3v to +0.3v lx total rms current ........................................................... 4a output short-circuit duration .................................... continuous continuous power dissipation (t a = +70oc) (multilayer board) tqfn (derate 30.3mw/oc above t a = +70oc) ...... 2424.2mw operating temperature range .......................... -40 n c to +125oc junction temperature ...................................................... +150oc storage temperature range ............................. -65 n c to +160oc lead temperature (soldering, 10s) ................................. +300oc soldering temperature (reflow) ....................................... +260oc stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to ab solute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) tqfn junction-to-ambient thermal resistance ( ja ) .......... 33oc/w junction-to-case thermal resistance ( jc ) ................. 2 o c/w absolute maximum ratings parameter symbol conditions min typ max units input supply (v in ) input voltage range v in 4.5 60 v input shutdown current i in-sh v en/uvlo = 0v (shutdown mode) 2.8 4.5 a input quiescent current i q_pfm v fb = 1v, mode = rt = open 118 v fb = 1v, mode = open 162 i q-dcm dcm mode, v lx = 0.1v 1.16 1.8 ma i q_pwm normal switching mode, f sw = 500khz, v fb = 0.8v 9.5 enable/uvlo (en/uvlo) en/uvlo threshold v enr v en/uvlo rising 1.19 1.215 1.24 v v enf v en/uvlo falling 1.068 1.09 1.111 en/ uvlo input leakage current i en v en/uvlo = 0v, t a = +25 o c -50 0 +50 na ldo v cc output voltage range v cc 6v < v in < 60v, i vcc = 1ma 4.75 5 5.25 v 1ma i vcc 25ma v cc current limit i vcc-max v cc = 4.3v, v in = 6v 26.5 54 100 ma v cc dropout v cc-do v in = 4.5v, i vcc = 20ma 4.2 v v cc uvlo v cc_uvr v cc rising 4.05 4.2 4.3 v v cc_uvf v cc falling 3.65 3.8 3.9 MAX17505 4.5v-60v, 1.7a, high-effciency, synchronous step-down dc-dc converter with internal compensation www.maximintegrated.com
maxim integrated 3 electrical characteristics (continued) (v in = v en/uvlo = 24v, r rt = 40.2k i (500khz), c vcc = 2.2f, v pgnd = v sgnd = v mode = v sync = 0v, lx = ss = reset = open, v bst to v lx = 5v, v fb = 1v, t a = t j = -40oc to +125oc, unless otherwise noted. typical values are at t a = +25oc. all voltages are referenced to sgnd, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units power mosfet and bst driver high-side nmos on-resistance r ds-onh i lx = 0.3a 165 325 m i low-side nmos on-resistance r ds-onl i lx = 0.3a 80 150 m i lx leakage current i lx_lkg v lx = v in - 1v, v lx = v pgnd + 1v, t a = +25oc -2 +2 a soft-start (ss) charging current i ss v ss = 0.5v 4.7 5 5.3 a feedback (fb) fb regulation voltage v fb_reg mode = sgnd or v cc 0.89 0.9 0.91 v mode = open 0.89 0.915 0.936 fb input bias current i fb 0 < v fb < 1v, t a = +25 o c -50 +50 na mode mode threshold v m-dcm mode = v cc (dcm mode) v cc - 1.6 v v m-pfm mode = open (pfm mode) v cc / 2 v m-pwm mode = gnd (pwm mode) 1.4 current limit peak current-limit threshold i peak-limit 2.4 2.8 3.25 a runaway current-limit threshold i runaway-limit 2.9 3.4 3.9 a valley current-limit threshold i sink-limit mode = open/ v cc -0.16 0 +0.16 a mode = gnd -1.8 pfm current-limit threshold i pfm mode = open 0.6 0.75 0.9 a rt and sync switching frequency f sw r rt = 102k? 180 200 220 khz r rt = 40.2k? 475 500 525 r rt = 8.06k? 1950 2200 2450 r rt = open 460 500 540 sync frequency capture range f sw set by r rt 1.1 x f sw 1.4 x f sw khz MAX17505 4.5v-60v, 1.7a, high-effciency, synchronous step-down dc-dc converter with internal compensation www.maximintegrated.com
maxim integrated 4 electrical characteristics (continued) (v in = v en/uvlo = 24v, r rt = 40.2k i (500khz), c vcc = 2.2f, v pgnd = v sgnd = v mode = v sync = 0v, lx = ss = reset = open, v bst to v lx = 5v, v fb = 1v, t a = t j = -40oc to +125oc, unless otherwise noted. typical values are at t a = +25oc. all voltages are referenced to sgnd, unless otherwise noted.) (note 2) note 2: all limits are 100% tested at +25oc. limits over temperature are guaranteed by design. note 3: see the overcurrent protection/hiccup mode section for more details. parameter symbol conditions min typ max units sync pulse width 50 ns sync threshold v ih 2.1 v v il 0.8 fb undervoltage trip level to cause hiccup v fb-hicf 0.56 0.58 0.6 v hiccup timeout (note 3) 32,768 cycles minimum on-time t on-min 135 ns minimum off-time t off-min 140 160 ns lx dead time 5 ns reset reset output level low i reset = 10ma 0.4 v reset output leakage current t a = t j = +25 o c , v reset = 5.5v -0.1 +0.1 a fb threshold for reset assertion v fb-okf v fb falling 90.5 92 94 %v fb- reg fb threshold for reset deassertion v fb-okr v fb rising 93.8 95 97.2 %v fb- reg reset deassertion delay after fb reaches 95% regulation 1024 cycles thermal shutdown thermal-shutdown threshold temperature rising 165 oc thermal-shutdown hysteresis 10 o c MAX17505 4.5v-60v, 1.7a, high-effciency, synchronous step-down dc-dc converter with internal compensation www.maximintegrated.com
maxim integrated 5 typical operating characteristics (v in = v en/uvlo = 24v, v pgnd = v sgnd = 0v, c vin = c vcc = 2.2f, c bst = 0.1f, c ss = 5600pf, rt = mode = open, t a = t j = -40oc to +125oc, unless otherwise noted. typical values are at t a = +25oc. all voltages are referenced to gnd, unless otherwise noted.) 40 50 60 70 80 90 100 0 500 1000 1500 efficiency (%) load current (ma) 5v output, pwm mode, figure 3 circuit, efficiency vs. load current v in =48v v in =36v v in =24v v in =12v mode = sgnd toc01 1700 0 10 20 30 40 50 60 70 80 90 100 0 500 1000 1500 efficiency (%) load current (ma) 3.3v output, pwm mode, figure 4 circuit, efficiency vs. load current v in =48v v in =36v v in =24v v in =12v mode = sgnd toc02 1700 30 40 50 60 70 80 90 100 1 10 100 1000 efficiency (%) load current (ma) 5v output, pfm mode, figure 3 circuit, efficiency vs. load current v in =48v v in =36v v in =24v v in =12v mode = open 1700 toc03 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 efficiency (%) load current (ma) 3.3v output, pfm mode, figure 4 circuit, efficiency vs. load current v in =48v v in =36v v in =24v v in =12v mode = open 1700 toc04 30 40 50 60 70 80 90 100 1 10 100 1000 efficiency (%) load current (ma) 5v output, dcm mode, figure 3 circuit, efficiency vs. load current v in =48v v in =36v v in =24v v in =12v mode = vcc 1700 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 efficiency (%) load current (ma) 3.3v output, dcm mode, figure 4 circuit, efficiency vs. load current v in =48v v in =36v v in =24v v in =12v mode = vcc 1700 toc06 4.95 4.96 4.97 4.98 4.99 5 5.01 5.02 5.03 5.04 5.05 0 500 1000 1500 output voltage (v) load current (ma) 5v output, pwm mode, figure 3 circuit, load and line regulation v in =48v v in =36v v in =24v v in =12v toc07 mode = sgnd 1700 3.26 3.27 3.28 3.29 3.3 3.31 3.32 3.33 3.34 3.35 3.36 0 500 1000 1500 output voltage (v) load current (ma) 3.3 v output, pwm mode, figure 4 circuit, load and line regulation v in =36v v in =48v v in =24v v in =12v toc08 mode = sgnd 1700 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5 0 500 1000 1500 output voltage (v) load current (ma) 5v output, pfm mode, figure 3 circuit, load and line regulation v in =36v v in =48v v in =24v v in =12v toc09 mode = open 1700 MAX17505 4.5v-60v, 1.7a, high-effciency, synchronous step-down dc-dc converter with internal compensation www.maximintegrated.com
maxim integrated 6 typical operating characteristics (continued) (v in = v en/uvlo = 24v, v pgnd = v sgnd = 0v, c vin = c vcc = 2.2f, c bst = 0.1f, c ss = 5600pf, rt = mode = open, t a = t j = -40oc to +125oc, unless otherwise noted. typical values are at t a = +25oc. all voltages are referenced to gnd, unless otherwise noted.) 3.27 3.28 3.29 3.3 3.31 3.32 3.33 3.34 3.35 3.36 3.37 0 500 1000 1500 output voltage (v) load current (ma) 3.3 v output, pfm mode, figure 4 circuit, load and line regulation v in =36v v in =48v v in =12v v in =24v toc10 mode = open 1700 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 0 20 40 60 80 100 switching frequency (khz) r rt (k ) switching frequency vs. rt resistance toc11 1a/div 1ms/div v en/uvlo 2v/div soft - start/shutdown from en/uvlo 5v output, 1.7a load current, figure 3 circuit toc12 v out 2v/div v reset 5v/div i out 1a / d i v 1 m s/ d i v v en / uv l o 2v / d i v s o f t - s t ar t / s hu t d o w n f r o m e n / u v l o 3 . 3 v o u t p u t , 1 . 7 a l o ad curr e n t , f ig ur e 4 c i rcu i t t o c 13 v o u t 2v / d i v v rese t 5v / d i v i o u t 2 m s / d i v v e n / u v l o 2 v / d i v s o f t - s t a r t / s h u t d o w n f r o m e n / u v l o 5 v o u t p u t , p f m m o d e , 5 ma l o a d c u r r e n t , f i g u r e 3 c i r c u i t t o c 14 v o u t 1 v / d i v v r e s e t 5 v / d i v m o d e = o p e n 2 m s/ d i v v en / uv l o 2v / d i v s o f t - s t ar t / s hu t d o w n f r o m e n / u v l o, 3 . 3 v o u t p u t , p f m m o d e , 5 ma l o ad curr e n t , f ig ur e 4 c i rcu i t t o c 15 v o u t 1v / d i v v rese t 5v / d i v m o d e = o pe n 1 m s / d i v v e n / u v l o 2 v / d i v s o f t - s t a r t w i t h 2 . 5 v p r e b i a s , 5 v o u t p u t , p w m m o d e f i g u r e 3 c i r c u i t t o c 16 v o u t 2 v / d i v v r e s e t 5 v / d i v m o d e = s g n d 1 m s/ d i v v e n / u v l o 2 v / d i v s o f t - s t a r t w i t h 2 . 5 v p r e b i a s 3 . 3 v o u t p u t , p f m m o d e , f i g u re 4 c i rc u i t t o c 17 v o u t 1 v / d i v v r es et 5 v / d i v m o d e = o p e n MAX17505 4.5v-60v, 1.7a, high-effciency, synchronous step-down dc-dc converter with internal compensation www.maximintegrated.com
maxim integrated 7 typical operating characteristics (continued) (v in = v en/uvlo = 24v, v pgnd = v sgnd = 0v, c vin = c vcc = 2.2f, c bst = 0.1f, c ss = 5600pf, rt = mode = open, t a = t j = -40oc to +125oc, unless otherwise noted. typical values are at t a = +25oc. all voltages are referenced to gnd, unless otherwise noted.) 1 s/div v out (ac) 20mv/div steady - state switching waveforms 5v output, 1.7a load current, figure 3 circuit toc18 v lx 10v/div i lx 1a/div 1 0 s/ d i v v o u t ( a c ) 100 m v / d i v s t e ad y - s t a t e s w i t ch i n g w a ve f o r ms , 5 v o u t p u t , p f m m o d e , 2 5 ma l o ad , f ig ur e 3 c i rcu i t t o c 20 v l x 10v / d i v i l x 500 m a / d i v m o d e = o pe n 1a/div 40 s/div v out (ac) 100mv/div 5v output, pwm mode, figure 3 circuit (load current stepped from 0.85 a to 1.7a) toc22 i out 1 s/ d i v v o u t ( a c ) 20 m v / d i v s t e ad y - s t a t e s w i t ch i n g w a ve f o r ms 5 v o u t p u t , p w m m o d e , n o l o ad , f ig ur e 3 c i rcu i t t o c 19 v l x 10v / d i v i l x 1a / d i v m o d e = sgnd 1 s/ d i v v o u t ( a c ) 20 m v / d i v s t e ad y - s t a t e s w i t ch i n g w a ve f o r ms , 5 v o u t p u t , dc m m o d e , 2 5 ma l o ad , f ig ur e 3 c i rcu i t t o c 21 v l x 10v / d i v i l x 200 m a / d i v m o d e = vcc 1a/div 100 s/div v out (ac) 50mv/div 3.3v output, pwm mode, figure 4 circuit (load current stepped from 0.85 a to 1.7a) toc23 i out MAX17505 4.5v-60v, 1.7a, high-effciency, synchronous step-down dc-dc converter with internal compensation www.maximintegrated.com
maxim integrated 8 typical operating characteristics (continued) (v in = v en/uvlo = 24v, v pgnd = v sgnd = 0v, c vin = c vcc = 2.2f, c bst = 0.1f, c ss = 5600pf, rt = mode = open.,t a = t j = -40oc to +125oc, unless otherwise noted. typical values are at t a = +25oc. all voltages are referenced to gnd, unless otherwise noted.) 500ma/div 40 s/div v out (ac) 100mv/div 5v output, pwm mode, figure 3 circuit (load current stepped from no load to 0.85a) toc24 i out mode = sgnd 500ma/div 2ms/div v out (ac) 100mv/div 5v output, pfm mode, figure 3 circuit (load current stepped from 5 ma to 0.85a) toc26 i out mode = open 500ma/div 200 s/div v out (ac) 100mv/div 5v output, dcm mode, figure 3 circuit (load current stepped from 50 ma to 0.85a) toc28 i out mode = vcc 500ma/div 100 s/div v out (ac) 50mv/div 3.3v output, pwm mode, figure 4 circuit (load current stepped from no load to 0.85a) toc25 i out mode = sgnd 500ma/div 2ms/div v out (ac) 100mv/div 3.3v output, pfm mode, figure 4 circuit (load current stepped from 5 ma to 0.85a) toc27 i out mode = open 500ma/div 200 s/div v out (ac) 100mv/div 3.3v output, dcm mode, figure 4 circuit (load current stepped from 50 ma to 0.85a) toc29 i out mode = vcc MAX17505 4.5v-60v, 1.7a, high-effciency, synchronous step-down dc-dc converter with internal compensation www.maximintegrated.com
maxim integrated 9 typical operating characteristics (continued) (v in = v en/uvlo = 24v, v pgnd = v sgnd = 0v, c vin = c vcc = 2.2f, c bst = 0.1f, c ss = 5600pf, rt = mode = open, t a = t j = -40oc to +125oc, unless otherwise noted. typical values are at t a = +25oc. all voltages are referenced to gnd, unless otherwise noted.) 1a/div 20ms/div v out 2v/div overload protection 5v output, figure 3 circuit toc30 i out p hase ( ) g a i n ( db ) fr e q u e n c y ( h z) t o c 32 5 v o u t p u t , 1 . 7 a l o a d c u r r e n t b o d e p l o t , f i g u r e 3 c i r cu i t g a in c r o s s o v e r fr e q u e n c y = 6 0 . 7 k k h z, p h a s e m a r g in = 5 9 p h a s e 2v/div 2 s/div v lx 10v/div application of external clock at 700 k h z 5v output, figure 3 circuit toc31 v sync g a i n ( db ) fr e q u e n c y ( h z ) t o c 33 3 . 3 v o ut p u t , 1 . 7 a l o a d cur r e n t , bo d e p l o t , f i g u r e 4 c i rc u i t c r o s s o v e r fr e q u e n c y = 58k h z , p h ase m a r g i n = 5 9 p h a s e g a in p hase ( ) MAX17505 4.5v-60v, 1.7a, high-effciency, synchronous step-down dc-dc converter with internal compensation www.maximintegrated.com
maxim integrated 10 pin description pin confguration pin name function 1C3 v in power-supply input. 4.5v to 60v input supply range. connect the v in pins together. decouple to pgnd with a 2.2f capacitor; place the capacitor close to the v in and pgnd pins. refer to the MAX17505 ev kit data sheet for a layout example. 4 en/uvlo enable/undervoltage lockout. drive en/uvlo high to enable the output voltage. connect to the center of the resistor-divider between v in and sgnd to set the input voltage at which the device turns on. pull up to v in for always-on operation. 5 reset open-drain reset output. the reset output is driven low if fb drops below 92% of its set value. reset goes high 1024 clock cycles after fb rises above 95% of its set value. 6 sync the device can be synchronized to an external clock using this pin. see the external frequency synchronization section for more details. 7 ss soft-start input. connect a capacitor from ss to sgnd to set the soft-start time. 8 cf at switching frequencies lower than 500khz, connect a capacitor from cf to fb. leave cf open if switching frequency is equal or more than 500khz. see the loop compensation section for more details. 9 fb feedback input. connect fb to the center tap of an external resistor-divider from the output to gnd to set the output voltage. see the adjusting output voltage section for more details. 10 rt connect a resistor from rt to sgnd to set the regulators switching frequency. leave rt open for the default 500khz frequency. see the setting the switching frequency (rt) section for more details. 11 mode mode pin confgures the device to operate either in pwm, pfm, or dcm modes of operation. leave mode unconnected for pfm operation (pulse skipping at light loads). connect mode to sgnd for constant-frequency pwm operation at all loads. connect mode to v cc for dcm operation. see the mode setting section for more details. 19 20 * exposed pad (connect to ground). 18 17 7 6 8 v in reset 9 v in pgnd v cc mode pgnd 12 lx 45 15 14 12 11 lx bst fb cf ss sync + v in sgnd 3 13 lx 16 10 rt pgnd tqf n 4mm 4mm MAX17505 top view en/uvl o MAX17505 4.5v-60v, 1.7a, high-effciency, synchronous step-down dc-dc converter with internal compensation www.maximintegrated.com
maxim integrated 11 pin description (continued) block diagram pin name function 12 v cc 5v ldo output. bypass v cc with 2.2f ceramic capacitance to sgnd. 13 sgnd analog ground 14C16 pgnd power ground. connect the pgnd pins externally to the power ground plane. connect the sgnd and pgnd pins together at the ground return path of the v cc bypass capacitor. refer to the MAX17505 ev kit data sheet for a layout example. 17C19 lx switching node. connect lx pins to the switching side of the inductor. refer to the MAX17505 ev kit data sheet for a layout example. 20 bst boost flying capacitor. connect a 0.1f ceramic capacitor between bst and lx. ep exposed pad. connect to the sgnd pin. connect to a large copper plane below the ic to improve heat dissipation capability. add thermal vias below the exposed pad. refer to the MAX17505 ev kit data sheet for a layout example. v cc sgnd 1.215v 5v lx pgnd mode v in bst ldo en/uvlo rt MAX17505 sync cf fb ss fb oscillator switchover logic error amplifier/ loop compensation mode selection logic slope compensation reset logic current-sense logic hiccup hiccup 5a v cc pwm/ pfm/ hiccup logic and drivers v bg = 0.9v reset en/uvlo MAX17505 4.5v-60v, 1.7a, high-effciency, synchronous step-down dc-dc converter with internal compensation www.maximintegrated.com
maxim integrated 12 detailed description the MAX17505 high-efficiency, high-voltage, synchro - nously rectified step-down converter with dual integrated mosfets operates over a 4.5v to 60v input. it delivers up to 1.7a and 0.9v to 90%v in output voltage. built-in compensation across the output voltage range eliminates the need for external components. the feedback (fb) regulation accuracy over -40 n c to +125 n c is 1.1%. the device features a peak-current-mode control architecture. an internal transconductance error amplifier produces an integrated error voltage at an internal node, which sets the duty cycle using a pwm comparator, a high- side current-sense amplifier, and a slope-compensation generator. at each rising edge of the clock, the high- side mosfet turns on and remains on until either the appropriate or maximum duty cycle is reached, or the peak current limit is detected. during the high-side mosfets on-time, the inductor current ramps up. during the second half of the switching cycle, the high-side mosfet turns off and the low-side mosfet turns on. the inductor releases the stored energy as its current ramps down and provides current to the output. the device features a mode pin that can be used to operate the device in pwm, pfm, or dcn control schemes. the device integrates adjustable-input undervoltage lockout, adjustable soft-start, open reset , and external frequency synchronization features. mode selection (mode) the logic state of the mode pin is latched when v cc and en/uvlo voltages exceed the respective uvlo rising thresholds and all internal voltages are ready to allow lx switching. if the mode pin is open at power-up, the device operates in pfm mode at light loads. if the mode pin is grounded at power-up, the device operates in constant-frequency pwm mode at all loads. finally, if the mode pin is connected to v cc at power-up, the device operates in constant-frequency dcm mode at light loads. state changes on the mode pin are ignored during normal operation. pwm mode operation in pwm mode, the inductor current is allowed to go negative. pwm operation provides constant frequency operation at all loads, and is useful in applications sensitive to switching frequency. however, the pwm mode of operation gives lower efficiency at light loads compared to pfm and dcm modes of operation. pfm mode operation pfm mode of operation disables negative inductor current and additionally skips pulses at light loads for high efficiency. in pfm mode, the inductor current is forced to a fixed peak of 750ma every clock cycle until the output rises to 102.3% of the nominal voltage. once the output reaches 102.3% of the nominal voltage, both the high-side and low-side fets are turned off and the device enters hibernate operation until the load discharges the output to 101.1% of the nominal voltage. most of the internal blocks are turned off in hibernate operation to save quiescent current. after the output falls below 101.1% of the nominal voltage, the device comes out of hibernate operation, turns on all internal blocks, and again commences the process of delivering pulses of energy to the output until it reaches 102.3% of the nominal output voltage. the advantage of the pfm mode is higher efficiency at light loads because of lower quiescent current drawn from supply. the disadvantage is that the output-voltage ripple is higher compared to pwm or dcm modes of operation and switching frequency is not constant at light loads. dcm mode operation dcm mode of operation features constant frequency operation down to lighter loads than pfm mode, by not skipping pulses but only disabling negative inductor cur - rent at light loads. dcm operation offers efficiency perfor - mance that lies between pwm and pfm modes. linear regulator (v cc ) an internal linear regulator (v cc ) provides a 5v nominal supply to power the internal blocks and the low-side mosfet driver. the output of the linear regulator (v cc ) should be bypassed with a 2.2f ceramic capacitor to sgnd. the device employs an undervoltage lockout circuit that disables the internal linear regulator when v cc falls below 3.8v (typ). setting the switching frequency (rt) the switching frequency of the device can be programmed from 200khz to 2.2mhz by using a resistor connected from the rt pin to sgnd. the switching frequency (f sw ) is related to the resistor connected at the rt pin (r rt ) by the following equation: 3 rt sw 21 10 r 1.7 f ?? where r rt is in k and f sw is in khz. leaving the rt pin open causes the device to operate at the default switching frequency of 500khz. see table 1 for rt resistor values for a few common switching frequencies. MAX17505 4.5v-60v, 1.7a, high-effciency, synchronous step-down dc-dc converter with internal compensation www.maximintegrated.com
maxim integrated 13 operating input voltage range the minimum and maximum operating input voltages for a given output voltage should be calculated as follows: out out(max) dcr in(min) sw(max) off(max) out(max) v (i (r 0.15)) v 1- (f t ) (i 0.175) + + = + out in(max) sw(max) on(min) v v f t) = where v out is the steady-state output voltage, i out (max) is the maximum load current, r dcr is the dc resistance of the inductor, f sw(max) is the maximum switching frequency, t off-max is the worst-case minimum switch off-time (160ns), and t on-min is the worst-case minimum switch on-time (135ns). external frequency synchronization (sync) the internal oscillator of the device can be synchronized to an external clock signal on the sync pin. the external synchronization clock frequency must be between 1.1 x f sw and 1.4 x f sw , where f sw is the frequency programmed by the rt resistor. the minimum external clock pulse-width high should be greater than 50ns. see the rt and sync section in the electrical characteristics table for details. overcurrent protection/hiccup mode the device is provided with a robust overcurrent protection scheme that protects the device under overload and output short-circuit conditions. a cycle-by-cycle peak current limit turns off the high-side mosfet whenever the high-side switch current exceeds an internal limit of 2.8a (typ). a runaway current limit on the high-side switch current at 3.4a (typ) protects the device under high input voltage, short-circuit conditions when there is insufficient output voltage available to restore the inductor current that was built up during the on period of the step-down converter. one occurrence of the runaway current limit triggers a hiccup mode. in addition, if due to a fault condition, feedback voltage drops to 0.58v (typ) any time after soft-start is complete, and hiccup mode is triggered. in hiccup mode, the converter is protected by suspending switching for a hiccup timeout period of 32,768 clock cycles. once the hiccup timeout period expires, soft-start is attempted again. note that when soft- start is attempted under overload condition, if feedback voltage does not exceed 0.58v, the device switches at half the programmed switching frequency. hiccup mode of operation ensures low power dissipation under output short-circuit conditions. reset output the device includes a reset comparator to monitor the output voltage. the open-drain reset output requires an external pullup resistor. reset goes high (high impedance) 1024 switching cycles after the regulator output increases above 95% of the designed nominal regulated voltage. reset goes low when the regulator output voltage drops to below 92% of the nominal regulated voltage. reset also goes low during thermal shutdown. prebiased output when the device starts into a prebiased output, both the high-side and the low-side switches are turned off so that the converter does not sink current from the output. high- side and low-side switches do not start switching until the pwm comparator commands the first pwm pulse, at which point switching commences. the output voltage is then smoothly ramped up to the target value in alignment with the internal reference. thermal-shutdown protection thermal-shutdown protection limits total power dissipation in the device. when the junction temperature of the device exceeds +165oc, an on-chip thermal sensor shuts down the device, allowing the device to cool. the thermal sensor turns the device on again after the junction temperature cools by 10oc. soft-start resets during thermal shutdown. carefully evaluate the total power dissipation (see the power dissipation section) to avoid unwanted triggering of the thermal shutdown in normal operation. table 1. switching frequency vs. rt resistor switching frequency (khz) rt resistor (k) 500 open 200 102 400 49.9 1000 19.1 2200 8.06 MAX17505 4.5v-60v, 1.7a, high-effciency, synchronous step-down dc-dc converter with internal compensation www.maximintegrated.com
maxim integrated 14 applications information input capacitor selection the input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuits switching. the input capacitor rms current requirement (i rms ) is defined by the following equation: = out in out rms out(max) in v (v - v ) ii v where, i out(max) is the maximum load current. i rms has a maximum value when the input voltage equals twice the output voltage (v in = 2 x v out ), so i rms(max) = i out(max) /2. choose an input capacitor that exhibits less than +10oc temperature rise at the rms input current for optimal long-term reliability. use low-esr ceramic capacitors with high-ripple-current capability at the input. x7r capacitors are recommended in industrial applications for their temperature stability. calculate the input capacitance using the following equation: = ? ? out(max) in sw in i d (1 - d) c fv where d = v out /v in is the duty ratio of the controller, f sw is the switching frequency, v in is the allowable input voltage ripple, and e is the efficiency. in applications where the source is located distant from the device input, an electrolytic capacitor should be added in parallel to the ceramic capacitor to provide necessary damping for potential oscillations caused by the inductance of the longer input power path and input ceramic capacitor. inductor selection three key inductor parameters must be specified for operation with the device: inductance value (l), inductor saturation current (i sat ), and dc resistance (r dcr ). the switching frequency and output voltage determine the inductor value as follows: out sw v l f = where v out , and f sw are nominal values. select an inductor whose value is nearest to the value calculated by the previous formula. select a low-loss inductor closest to the calculated value with acceptable dimensions and having the lowest possible dc resistance. the saturation current rating (i sat ) of the inductor must be high enough to ensure that saturation can occur only above the peak current-limit value of 2.8a. output capacitor selection x7r ceramic output capacitors are preferred due to their stability over temperature in industrial applications. the output capacitors are usually sized to support a step load of 50% of the maximum output current in the application, so the output voltage deviation is contained to 3% of the output voltage change. the minimum required output capacitance can be calculated as follows: = ? step response out out it 1 c 2v ?+ response c sw 0.33 1 t () ff where i step is the load current step, t response is the response time of the controller, d v out is the allowable output-voltage deviation, f c is the target closed-loop crossover frequency, and f sw is the switching frequency. select f c to be 1/9th of f sw if the switching frequency is less than or equal to 500khz. if the switching frequency is more than 500khz, select f c to be 55khz. soft-start capacitor selection the device implements adjustable soft-start operation to reduce inrush current. a capacitor connected from the ss pin to sgnd programs the soft-start time. the selected output capacitance (c sel ) and the output voltage (v out ) determine the minimum required soft-start capacitor as follows: -6 ss sel out c 28 10 c v ? the soft-start time (t ss ) is related to the capacitor connected at ss (c ss ) by the following equation: ss ss -6 c t 5.55 10 = for example, to program a 1ms soft-start time, a 5.6nf capacitor should be connected from the ss pin to sgnd. setting the input undervoltage-lockout level the device offers an adjustable input undervoltage-lockout level. set the voltage at which the device turns on with a resistive voltage-divider connected from v in to sgnd. connect the center node of the divider to en/uvlo. choose r1 to be 3.3m i and then calculate r2 as follows: = inu r1 1.215 r2 (v - 1.215) where v inu is the voltage at which the device is required to turn on. ensure that v inu is higher than 0.8 x v out . MAX17505 4.5v-60v, 1.7a, high-effciency, synchronous step-down dc-dc converter with internal compensation www.maximintegrated.com
maxim integrated 15 loop compensation the device is internally loop compensated. however, if the switching frequency is less than 500khz, connect a 0402 capacitor c6 between the cf pin and the fb pin. use table 2 to select the value of c6. adjusting output voltage set the output voltage with a resistive voltage-divider connected from the positive terminal of the output capacitor (v out ) to sgnd (see figure 2). connect the center node of the divider to the fb pin. use the following procedure to choose the resistive voltage-divider values: calculate resistor r3 from the output to the fb pin as follows: 3 c out 216 10 r3 fc = where r3 is in k, crossover frequency f c is in khz, and the output capacitor c out is in f. choose f c to be 1/9th of the switching frequency, f sw , if the switching frequency is less than or equal to 500khz. if the switching frequency is more than 500khz, select f c to be 55khz. calculate resistor r4 from the fb pin to sgnd as follows: = out r3 0.9 r4 (v - 0.9) power dissipation ensure that the junction temperature of the device does not exceed 125oc under the operating conditions specified for the power supply. at a particular operating condition, the power losses that lead to temperature rise of the part are estimated as follows: ( ) = 2 loss out dcr out 1 p (p ( - 1) ) - i r = out out out p vi where p out is the total output power, is the efficiency of the converter, and r dcr is the dc resistances of the inductor. (see the typical operating characteristics for more information on efficiency at typical operating conditions.) for a multilayer board, the thermal performance metrics for the package are given below: ja 33 c w = jc 2cw = the junction temperature of the device can be estimated at any given maximum ambient temperature (t a_max ) from the equation below: ( ) = + j_max a _max ja loss tt p if the application has a thermal management system that ensures that the exposed pad of the device is maintained at a given temperature (t ep_max ) by using proper heat sinks, then the junction temperature of the device can be estimated at any given maximum ambient temperature from the equation below: ( ) = + j_max ep_max jc loss tt p figure 1. setting the input undervoltage lockout figure 2. setting the output voltage table 2. c6 capacitor value at various switching frequencies switching frequency range (khz) c6 (pf) 200 to 300 2.2 300 to 400 1.2 400 to 500 0.75 r3 r4 sgnd fb v out r1 r2 sgnd en/uvlo v in MAX17505 4.5v-60v, 1.7a, high-effciency, synchronous step-down dc-dc converter with internal compensation www.maximintegrated.com
maxim integrated 16 pcb layout guidelines all connections carrying pulsed currents must be very short and as wide as possible. the inductance of these connections must be kept to an absolute minimum due to the high di/dt of the currents. since inductance of a current carrying loop is proportional to the area enclosed by the loop, if the loop area is made very small, inductance is reduced. additionally, small-current loop areas reduce radiated emi. a ceramic input filter capacitor should be placed close to the v in pins of the ic. this eliminates as much trace inductance effects as possible and gives the ic a cleaner voltage supply. a bypass capacitor for the v cc pin also should be placed close to the pin to reduce effects of trace impedance. when routing the circuitry around the ic, the analog small-signal ground and the power ground for switching currents must be kept separate. they should be connected together at a point where switching activity is at a minimum, typically the return terminal of the v cc bypass capacitor. this helps keep the analog ground quiet. the ground plane should be kept continuous/unbroken as far as possible. no trace carrying high switching current should be placed directly over any ground plane discontinuity. pcb layout also affects the thermal performance of the design. a number of thermal vias that connect to a large ground plane should be provided under the exposed pad of the part, for efficient heat dissipation. for a sample layout that ensures first pass success, refer to the MAX17505 evaluation kit layout available at www.maximintegrated.com . typical application circuit reset v in v in v in bst rt sync mode v cc sgnd cf ss fb pgnd pgnd pgnd lx lx lx en/uvlo MAX17505 l1 10h c5 0.1f c4 22f r3 178k? r4 39k? v out 5v, 1.7a v in (6.5v to 60v) c1 2.2f c3 5.6nf c2 2.2f f sw = 500khz figure 3 MAX17505 4.5v-60v, 1.7a, high-effciency, synchronous step-down dc-dc converter with internal compensation www.maximintegrated.com
maxim integrated 17 package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: bicmos note: device operates over the -40oc to +125oc temperature range, unless otherwise noted. +denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. ordering information typical application circuit (continued) part pin-package MAX17505atp+ 20 tqfn (4mm x 4mm) package type package code outline no. land pattern no. 20 tqfn-ep t2044+4 21-0139 90-0409 reset v in v in v in bst rt sync mode v cc sgnd cf ss fb pgnd pgnd pgnd lx lx lx v in (4.5v to 60v) en/uvlo MAX17505 l1 6.8h c5 0.1f c4 47f r3 127k? r4 47.5k? v out 3.3v, 1.7a c1 2.2uf c3 5600pf c2 2.2f f sw = 500khz v in figure 4 MAX17505 4.5v-60v, 1.7a, high-effciency, synchronous step-down dc-dc converter with internal compensation www.maximintegrated.com
? 2014 maxim integrated products, inc. 18 revision history revision number revision date description pages changed 0 1/14 initial release maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifcations without notice at any time. the parametric values (min and max limits) shown in the electrical character - istics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maximintegrated.com. MAX17505 4.5v-60v, 1.7a, high-effciency, synchronous step-down dc-dc converter with internal compensation

▲Up To Search▲

Price & Availability of MAX17505

	To Download MAX17505 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .